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A New Technique to Extract the Gate Bias Dependent S/D Series Resistance of Sub-100nm MOSFETs

by admin on April 28th, 2009

A New Technique to Extract the Gate Bias Dependent S/D Series Resistance of Sub-100nm MOSFETs
D. Fleury, A. Cros, G. Bidal, H. Brut, E. Josse and G. Ghibaudo
In Proceedings of the 2009 International Symposium on VLSI Technology, Systems and Applications – BEST STUDENT PAPER AWARD

ABSTRACT: In this study, a new technique to extract the S/D series resistance (Rsd) from the total resistance versus transconductance gain plot Rtot(1/β) is proposed. The technique only requires the measurement of Id(Vgs)|Vgt and beta, allowing fast and statistical analysis in an industrial context. Unlike the usual Rtot(L)-based techniques, it has the advantage of being insensitive to the channel length and mobility variations and finally enables to extract very accurate values for Rsd(Vgs) and the effective mobility reduction factor µeff(Vgt)/μeff(0).

[Full paper] (full-text article)

[Presentation material] (presentation material)

This paper appears in: VLSI Technology, Systems, and Applications, 2009. VLSI-TSA ’09. International Symposium on

Publication Date: 27-29 April 2009
On page(s): 109 – 110
Location:
Hsinchu (Taiwan)
ISSN:
1930-885X
Print ISBN:
978-1-4244-2784-0
INSPEC Accession Number:
10750580
Digital Object Identifier:
10.1109/VTSA.2009.5159314
Current Version Published:
07 juillet 2009

Copyright © 2009 IEEE. This material is posted here with permission of the IEEE. Internal or personal use of this material is permitted.  However, permission to preprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org

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