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Final version of my PhD thesis (in french)

by admin on March 5th, 2010

CONTRIBUTION TO THE EXPERIMENTAL STUDY OF TRANSPORT IN DECANANOMETRIC TRANSISTORS OF UB-45NM CMOS TECHNOLOGIES

Resume: The downscaling of electronic devices which allows a large-scale integration has been feasible thanks to many innovations regarding the fabrication processes. These changes deeply modify the electrical behavior of MOS transistors when the gate length becomes shorter than 100nm, altering the physical understanding of this device. This work deals with the study about advanced devices performances (sub-45nm technologies) and the analyze of electrical characteristics. Improvements of state-of-the-art methodologies and new extraction techniques are proposed for enabling the analysis of electrical parameters to be adapted to an industrial context, on very short devices. The use of these new techniques provides a better physical understanding which is required to predict the performances of future technologies.

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